A.always@（posedge clk）case （state ）0：next_state<=1；1：next_state<=x
B.always@（posedge clk）case （state ）0：if（a==0）next_state<=1；else next_state<=x；1：next_state<=x
C.always@（posedge clk）case （state ）0：if（state==0）next_state<=1；else next_state<=x；1：next_state<=x
D.以上都不對

A.parameter [2：0]s0=0，s1=1，s2=2，s3=3，s4=4；reg [2：0]current_state，next_state
B.parameter [1：0]s0=0，s1=1，s2=2，s3=3，s4=4；reg [1：0]current_state，next_state
C.TYPE FSM_ST IS （s0，s1，s2，s3，s4）；SIGNAL current_state，next_state：FSM_ST
D.typedef enum {s0，s1，s2，s3，s4}type_user；type_user current_state，next_state